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The CMP simulator
calculates the post-CMP film thickness profile across a die from its
GDSII file, the deposition thickness, and the CMP process conditions
using CTI's proprietary algorithm. The following is a sample result.
This picture show simulated results of variations of some key parameters during the polish
process. The x-axis is time in seconds. In the chart, Max step, ILD
variation, Max ILD, Min ILD, Wafer TIR and TIR stand for maximum step height, Inter-Lever Dielectric
(ILD) thickness variation, maximum ILD
thickness, minimum ILD thickness, wafer-level Total Indicated Range (TIR)
and die-level TIR respectively.
Key Benefits
 | Knows when step will be removed, when TIR will be within range before
doing experiment. |
| Time dependent data provides insights that are very difficulty to obtain
through experiments. |
| Allows intelligent choice of polish time to obtain best trade-off between
throughput and TIR. |
| The "wafter TIR" represents combined non-uniformity of
within-die non-uniformity (WIDNU) and within-wafer non-uniformity (WIWNU).
The proper trade-off can be obtained from the curve. |
Contact us
Please use the inquiry form to tell us
what you are interested.
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