Question: Why there is a turning point for the ILD variation in simulation result?

Answer: This is a very insightful question. In fact, no other model (simulator) is able to predict this phenomenon. Yet, this is the reality. Please see [1] for experimental evidence. An intuitive explanation is as following:

Let's imagine a simple layout with dense lines and sparse lines. Let's assume that after oxide deposition, their film profile heights are about the same (there will be small differences depending on how sparse the lines are). When polish starts, the sparse area will be polished faster than dense area, hence the height difference between dense and sparse areas increases. Once their height difference exceeds the amount that the pad can bend, the oxide removal will mostly come from dense area. This reduces the height difference, and sparse area will be polished again. Overall, the sparse area will maintain an lower height than the dense area during the whole process of polishing. Consequently, the ILD step height in sparse area will be removed earlier than that in dense area. Once that happens, the oxide density in sparse area will be equal or higher than dense area and will have smaller or equal removal rate than dense area. From then on, the height difference between sparse area and dense area will keep on decreasing until polish stops. Of course, two other factors will prevent us from keeping on polishing: one is throughput; the other is within-wafer uniformity, which deteriorates with polishing time.

Question: Can parasitic capacitance from dummy fill become an issue?

Answer: It's not an issue if a little bit care is taken. If you constrain dummy fill to be 3-5um away from metal lines, the intra-layer parasitic capacitance introduced by dummy fill is negligible. In fact, interconnect parasitic extraction tool won't even extract couplings between metal lines 3-5um away. For inter-layer parasitic capacitance, similar but less stringent constrains can be applied.

Another point to make is that Digital's Alpha chip and Intel's Pentium chip have been using dummy fill since their inception while their clock speed are the fastest of all IC chips. There had to be a good reason for their choice.

Question: Would smart-dummy be needed for 300 mm wafer?

Answer:  It is even more needed. Since the overall film thickness variation is the sum of within-die non-uniformity (WIDNU) and within-wafer non-uniformity (WIWNU), as one goes from 200 mm to 300 mm, the WIWNU increases, the overall non-uniformity budget does not change if all other conditions equal, that puts more stringent requirement for WIDNU. That's where smart-dummy come into play.

[1] "Improving within-die nonuniformity in dielectric CMP," by Taber Smith etc. CMPMIC 2000, pp362-364.

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